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plc18v8z zero standby power cmos versatile pal devices product specification replaces data sheet plc18v8z35/plc18v8zi of dec 19 1995, and data sheet plc18v8z25/plc18v8zi of dec 19, 1995 1997 aug 08 integrated circuits
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 2 1997 aug 08 8532016 18258 description the plc18v8z is a universal pal ? device featuring high performance and virtually zero-standby power for power sensitive applications. they are reliable, user-configurable substitutes for discrete ttl/cmos logic. while compatible with ttl and hct logic, the plc18v8z can also replace hc logic over the v cc range of 4.5 to 5.5v. the plc18v8z is a two-level logic element comprised of 10 inputs, 74 and gates (product terms) and 8 output macro cells. each output features an aoutput macro cello which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. as a result, the plc18v8z is capable of emulating all common 20-pin pal devices to reduce documentation, inventory, and manufacturing costs. a power-up reset function and a register preload function have been incorporated in the plc18v8z architecture to facilitate state machine design and testing. with a standby current of less than 100 m a and active power consumption of 1.5ma/mhz, the plc18v8z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers. the plc18v8z is also processed to industrial requirements for operation over an extended temperature range of -40 c to +85 c and supply voltage of 4.5v to 5.5v. ordering information can be found on the following page. features ? 20-pin universal programmable array logic ? virtually zero-standby-power 20 m a (typical) ? available in dip, plcc, sol (small outline), ssop (shrink small outline), and tssop (thin shrink small outline) packages ? functional replacement for series 20 pal devices i ol = 24ma ? up to 18 inputs and 8 input/output macro cells ? programmable output polarity ? power-up reset on all registers ? register preload capability ? synchronous preset/asynchronous reset ? security fuse to prevent duplication of proprietary designs ? also available in 3v operationthe p3c18v8z applications ? battery powered instruments ? laptop and pocket computers ? industrial control ? medical instruments ? portable communications equipment pin configurations sp00544 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d, db, dh, n, packages i0/clk i1 i2 i3 i4 i5 i6 i7 i8 f0 gnd f1 f2 f3 f4 f5 f6 f7 v cc i9/oe d = plasitc small outline large package (300mil-wide) db = plastic shrink small outline package (5.3mm wide) dh = plastic thin shrink small outline package (4.4mm wide) n = plastic dual in-line package (dip) (300mil-wide) 1 2 3 4 5 6 7 8 910111213 14 15 16 17 18 19 20 a package a = plastic leaded chip carrier f0 f1 f2 f3 f4 f5 f6 f7 v cc i9/ oe i0/ clk i1 i2 i3 i4 i5 i6 i7 i8 gnd pin descriptions i dedicated input b bidirectional input/output o dedicated output d registered output (d-type flip-flop) f output/input macrocell clk clock input oe output enable v cc supply voltage gnd ground pal is a registered trademark of advanced micro devices, inc.
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 3 ordering information description temperature range order code drawing number 20-pin (300mil-wide) plastic dual in-line package, 25ns t pd plc18v8z25n sot146-1 20-pin (350mil square) plastic leaded chip carrier package plc18v8z25a sot380-1 20-pin (300mil-wide) plastic small outline large package plc18v8z25d sot163-1 20-pin (5.3mm-wide) plastic shrink small outline package plc18v8z25db sot339-1 20-pin (4.4mm-wide) plastic thin shrink small outline package commercial te m p erature range plc18v8z25dh sot360-1 20pin (300milwide) plastic dual inline package. 35ns t pd t empera t ure r ange 5% power supplies plc18v8z35n sot1461 20pin (350mil square) plastic leaded chip carrier package plc18v8z35a sot3801 20pin (300mil square) plastic small outline large package package plc18v8z35d sot1631 20pin (5.3mmwide) plastic shrink small outline package plc18v8z35db sot3391 20pin (4.4mmwide) plastic thin shrink small outline package plc18v8z35dh sot2601 20-pin (300mil-wide) plastic dual in-line package 25ns t pd plc18v8zian sot146-1 20-pin (350mil square) plastic leaded chip carrier package plc18v8ziaa sot380-1 20-pin (300mil-wide) plastic small outline large package plc18v8ziad sot163-1 20-pin (5.3mm-wide) plastic shrink small outline package plc18v8ziadb sot339-1 20-pin (4.4mm-wide) plastic thin shrink small outline package industrial te m p erature range PLC18V8ZIADH sot360-1 20pin (300milwide) plastic dual inline package, 40ns t pd t empera t ure r ange 10% power supplies plc18v8zin sot1461 20pin (350mil square) plastic leaded chip carrier package plc18v8zia sot3801 20pin (300mil square) plastic small outline large package plc18v8zzid sot1631 20pin (5.3mmwide) plastic shrink small outline package plc18v8zidb sot3391 20pin (4.4mmwide) plastic thin shrink small outline package plc18v8zidh sot3601
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 4 pal device to plc18v8z output pin configuration cross reference pin no. plc 18v8z 16l8 16h8 16p8 16p8 16r4 16rp4 16r6 16rp6 16r8 16rp8 16l2 16h2 16p2 14l4 14h4 14p4 12l6 12h6 12p6 10l8 10h8 10p8 1 i 0 /clk i clk clk clk i i i i 19 f7 b b b d i i i o 18 f6 b b d d i i o o 17 f5 b d d d i o o o 16 f4 b d d d o o o o 15 f3 b d d d o o o o 14 f2 b d d d i o o o 13 f1 b b d d i i o o 12 f0 b b b d i i i o 11 i 9 /oe i oe oe oe i i i i the philips semiconductors' state-of-the-art floating-gate cmos eprom process yields bipolar equivalent performance at less than one-quarter the power consumption. the erasable nature of the eprom process enables philips semiconductors to functionally test the devices prior to shipment to the customer. additionally, this allows philips semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual eprom cell. 100% programming yield is subsequently guaranteed. functional diagram config. cell config. cell i 0 / clk i 1 i 2 i 7 i 8 programmable and array 36 rows x 72 columns f 6 f 1 f 0 i 9 /oe i 9 f 7 i 0 clk 9 9 9 9 omc oe omc omc omc sp ar sp00013
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 5 logic diagram pins 1 and 11 are configured as inputs 0 and 9, respectively, via the configuration cell. the clock and oe functions are disabled. all output macro cells (omc) are configured as bidirectional i/o, with the outputs disabled via the direc- tion term. denotes a programmable cell location. 1 2 3 4 5 6 7 8 9 notes: in the unprogrammed or virgin state: all cells are in a conductive state. all and gate locations are pulled to a logic a0o (low). output polarity is inverting. 0 4 8 12162024283235 sp ar clk oe ac1 ac2 dir clk f7 19 11 sp ar clk oe ac1 ac2 dir f6 18 sp ar clk oe ac1 ac2 dir f5 17 sp ar clk oe ac1 ac2 dir f4 16 sp ar clk oe ac1 ac2 dir f3 15 sp ar clk oe ac1 ac2 dir f2 14 sp ar clk oe ac1 ac2 dir f1 13 sp ar clk oe ac1 ac2 dir f0 12 sp ar i9/oe i0/clk i1 i2 i3 i4 i5 i6 i7 i8 i i i i 0 0 9 9 i i f f 8 8 0 0 i i f f 7 7 1 1 i i f f 6 6 2 2 i i f f 5 5 3 3 i i f f 4 4 4 4 i i f f 3 3 5 5 i i f f 2 2 6 6 i i f f 1 1 7 7 config. cell sp00012
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 6 output macro cell (omc) oe mux 1 11 clk q oe d f 00 11 10 01 out mux 10 00 01 11 f mux 00 10 11 01 v cc output polarity control from and array s x (n) direction control term to all omcs to all omcs { ac1 n ac2 n note: denotes a programmable cell location. from and array sp ar sp00014 the output macro cell (omc) the plc18v8z series devices have 8 individually programmable output macro cells. the 72 and inputs (or product terms) from the programmable and array are connected to the 8 omcs in groups of 9. eight of the and terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional i/o pin. two product terms are dedicated for the synchronous preset and asynchronous reset functions. each omc can be independently programmed via 16 architecture control bits, ac1 n and ac2 n (one pair per macro cell). similarly, each omc has a programmable output polarity control bit (xn). by configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. note that the configuration cell is automatically programmed based on the omc configuration. design security the plc18v8z series devices have a programmable security fuse that controls the access to the data programmed in the device. by using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 7 configuration cell a single configuration cell controls the functions of pins 1 and 11. refer to functional diagram. when the configuration cell is programmed, pin 1 is a dedicated clock and pin 11 is dedicated for output enable. when the configuration cell is unprogrammed, pins 1 and 11 are both dedicated inputs. note that the output enable for all registered omcs is commonefrom pin 11 only. output enable control of the bidirectional i/o omcs is provided from the and array via the direction product term. if any one omc is configured as registered, the configuration cell will be automatically configured (via the design software) to ensure that the clock and output enable functions are enabled on pins 1 and 11, respectively. if none of the omcs are registered, the configuration cell will be programmed such that pins 1 and 11 are dedicated inputs. the programming codes are as follows: pin 1 = clk, pin 11 = oe l pin 1 and pin 11 = input h control cell configurations function ac1 1 ac2 n config. cell comments registered mode programmed programmed programmed dedicated clock from pin 1. oe control for all registerd omcs from pin 11 only. bidirectional i/o mode 1 unprogrammed unprogrammed unprogrammed pins 1 and 11 are dedicated inputs. 3-state control from and array only. fixed input mode unprogrammed programmed unprogrammed pins 1 and 11 are dedicated inputs. fixed output mode programmed unprogrammed unprogrammed pins 1 and 11 are dedicated inputs. the feedback path (via f mux ) is disabled. note: 1. this is the virgin state as shipped from the factory. architecture controleac1 and ac2 i code d omc configuration registered (dtype) 1 11 s clk f(d), f (d ) q oe s f(b), f (b ) dir code b omc configuration code o omc configuration fixed output code configuration cell code l configuration cell code omc configuration fixed input bidirectional i/o 1 (combinatorial) pin 1 = clk pin 11 = oe h 6 pin 1 = input pin 11 = input s f(o), f (o ) f (i) f(d), f (d ) 11 1 clk q oe 11 1 clk q oe nc nc sp ar sp ar sp ar sp00015 notes: a factory shipped unprogrammed device is configured such that: 1. this is the initial unprogrammed state. all cells are in a conductive state. 2. all and gates are pulled to a logic a0o (low). 3. output polarity is inverting. 4. pins 1 and 11 are configured as inputs 0 and 9. the clock and oe functions are disabled. 5. all output macro cells (omcs) are configured as bidirectional i/o, with the outputs disabled via the direction term. 6. this configuration cannot be used if any omcs are configured as registered (code = d).
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 8 absolute maximum ratings 1 symbol parameter ratings unit v cc supply voltage 0.5 to +7 v dc v cc operating supply voltage 4.5 to 5.5 (industrial) 4.75 to 5.25 (commercial) v dc v in input voltage 0.5 to v cc + 0.5 v dc v out output voltage 0.5 to v cc + 0.5 v dc d t/ d v input/clock transition rise or fall 2 250 ns/v maximum i in input currents 10 to +10 ma i out output currents +24 ma t amb operating temperature range 40 to +85 (industrial) 0 to +75 (commercial) c t stg storage temperature range 65 to +150 c note: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implie d. 2. all digital circuits can oscillate or trigger prematurely when input rise and fall times are very long. when the input signa l to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, c an cause subsequent stages to switch and give erroneous results. for this reason, schmitt-triggers are recommended if rise/fall times are likely t o exceed 250ns at v cc = 4.5v. thermal ratings temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise ambient to junction 75 c ac test conditions +5v c l r 1 r 2 s 1 gnd b z b y inputs i 0 i 9 b w b x outputs c 2 c 1 dut note: c 1 and c 2 are to bypass v cc to gnd. v cc sp00006 voltage waveforms 90% 10% 5ns 5ns 5ns 5ns 90% 10% +3.0v +3.0v 0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00017
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 9 dc electrical characteristics commercial = 0 c t amb +75 c, 4.75v v cc 5.25v; industrial = 40 c t amb +85 c, 4.5v v cc 5.5v limits symbol parameter test condition min typ 1 max unit input voltage v il low v cc = min 0.3 0.8 v v ih high v cc = max 2.0 v cc + 0.3 v output voltage 2 v ol low v cc = min, i ol = 20 m a 0.100 v v ol low v cc = min, i ol = 24ma 0.500 v v oh high v cc = min, i oh = 3.2ma 2.4 v v oh high v cc = min, i oh = 20 m a v cc 0.1v v input current i il low 7 v in = gnd 10 m a i ih high v in = v cc 10 m a output current i o(off) hi-z state v out = v cc 10 m a i o(off) hi - z state v out = gnd 10 m a i os short-circuit 3 v out = gnd 130 ma i cc v cc supply current (standby) v cc = max, v in = 0 or v cc 8 20 100 m a i cc /f v cc supply current (active) 4 v cc = max (cmos inputs) 5, 6 1.5 ma/mhz capacitance c i input v cc = 5v, v in = 2.0v 12 pf c b i/o v b = 2.0v 15 pf f(mhz) 45 30 15 0 0 6 12 18 24 30 i cc (ma) 100 m a sp00018 figure 1. i cc vs frequency 5, 6 (worst case) 6 5 4 3 2 1 0 1 2 0 20 40 60 80 100 120 140 160 180 200 t pd output capacitance loading (pf) sp00019 figure 2. d t pd vs output capacitance loading (typical) notes: 1. all typical values are at v cc = 5v, t amb = +25 c. 2. all voltage values are with respect to network ground terminal. 3. duration of short-circuit should not exceed one second. test one at a time. 4. tested with ttl input levels: v il = 0.45v, v ih = 2.4v. measured with all outputs switching. 5. d i cc /ttl input = 2ma. 6. d i cc vs frequency (registered configuration) = 2ma/mhz. 7. i il for pin 1 (i 0 /clk) is 10 m a with v in = 0.4v. 8. v in includes clk and oe if applicable.
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 10 ac electrical characteristics 4 commercial = 0 c t amb +75 c, 4.75v v cc < 5.25v; industrial = 40 c t amb +85 c, 4.5v v cc 5.5v; r 2 = 390 w test condition 1 plc18v8z25 (commercial) plc18v8zia (industrial) symbol parameter from to r 1 ( w ) c l (pf) min max min max unit pulse width t ckp clock period (minimum t is + t cko ) clk + clk + 200 50 33 33 ns t ckh clock width high clk + clk 200 50 15 15 ns t ckl clock width low clk clk + 200 50 15 15 ns t arw async reset pulse width i , f i + , f + 25 25 ns hold time t ih input or feedback data hold time clk + input 200 50 0 0 ns setup time t is input or feedback data setup time i , f clk + 200 50 18 18 ns propagation delay t pd delay from input to active output i , f f 200 50 25 25 ns t cko clock high to output valid access time clk + f 200 50 15 15 ns t oe1 3 product term enable to outputs off i , f f active-high r = 1.5k active-low r = 550 50 25 25 ns t od1 2 product term disable to outputs off i , f f from v oh r = from v ol r = 200 5 25 25 ns t od2 2 pin 11 output disable high to outputs off oe f from v oh r = from v ol r = 200 5 20 20 ns t oe2 3 pin 11 output enable to active output oe + f active-high r = 1.5k active-low r = 550 50 20 20 ns t ard async reset delay i , f f + 30 30 ns t arr async reset recovery time i , f clk + 20 20 ns t spr sync preset recovery time i , f clk + 20 20 ns t ppr power-up reset v cc + f + 25 25 ns frequency of operation f max maximum frequency i/(t is + t cko ) 200 50 30 30 mhz notes: 1. refer also to ac test conditions. (test load circuit) 2. for 3-state output; output enable times are tested with c l = 50pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf. high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 3. resistor values of 1.5k and 550 w provide 3-state levels of 1.0v and 2.0v, respectively. output timing measurements are to 1.5v level. 4. leave all the cells on unused product terms intact (unprogrammed) for all patterns.
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 11 ac electrical characteristics 4 commercial = 0 c t amb +75 c, 4.75v v cc < 5.25v; industrial = 40 c t amb +85 c, 4.5v v cc 5.5v; r 2 = 390 w test condition 1 plc18v8z35 (commercial) plc18v8zi (industrial) symbol parameter from to r 1 ( w ) c l (pf) min max min max unit pulse width t ckp clock period (minimum t is + t cko ) clk + clk + 200 50 47 57 ns t ckh clock width high clk + clk 200 50 20 25 ns t ckl clock width low clk clk + 200 50 20 25 ns t arw async reset pulse width i , f i + , f + 35 40 ns hold time t ih input or feedback data hold time clk + input 200 50 0 0 ns setup time t is input or feedback data setup time i , f clk + 200 50 25 30 ns propagation delay t pd delay from input to active output i , f f 200 50 35 40 ns t cko clock high to output valid access time clk + f 200 50 22 27 ns t oe1 3 product term enable to outputs off i , f f active-high r = 1.5k active-low r = 550 50 35 40 ns t od1 2 product term disable to outputs off i , f f from v oh r = from v ol r = 200 5 35 40 ns t od2 2 pin 11 output disable high to outputs off oe f from v oh r = from v ol r = 200 5 25 40 ns t oe2 3 pin 11 output enable to active output oe + f active-high r = 1.5k active-low r = 550 50 25 30 ns t ard async reset delay i , f f + 35 40 ns t arr async reset recovery time i , f clk + 25 30 ns t spr sync preset recovery time i , f clk + 25 30 ns t ppr power-up reset v cc + f + 35 40 ns frequency of operation f max maximum frequency i/(t is + t cko ) 200 50 21 18 mhz notes: 1. refer also to ac test conditions. (test load circuit) 2. for 3-state output; output enable times are tested with c l = 50pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf. high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 3. resistor values of 1.5k and 550 w provide 3-state levels of 1.0v and 2.0v, respectively. output timing measurements are to 1.5v level. 4. leave all the cells on unused product terms intact (unprogrammed) for all patterns.
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 12 power-up reset in order to facilitate state machine design and testing, a power-up reset function has been incorporated in the plc18v8z. all internal registers will reset to active-low (logical a0o) after a specified period of time (t ppr ). therefore, any omc that has been configured as a registered output will always produce an active-high on the associated output pin because of the inverted output buffer. the internal feedback (q) of a registered omc will also be set low. the programmed polarity of omc will not affect the active-high output condition during a system power-up condition. timing diagrams switching waveforms valid input valid input 3state 3-state inputs i/o, reg. feedback clk pin 11 oe registered outputs any input programmed for direction control combinatorial outputs t is t ih t ckh t ckl t ckp t cko t od1 t od2 t oe2 t pd t oe1 power-up reset note: diagram presupposes that the outputs (f) are enabled. the reset occurs regardless of the output condition (enabled or disabled) . t ckp t ckh t ckl t is 1.5v 1.5v 1.5v t ckl t ih t is 1.5v 1.5v t cko 1.5v 1.5v t ppr 4.5v 3.0v +5v 0v v oh v ol +3v 0v +3v 0v v cc f (outputs) i, b (inputs) clk sp00020
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 13 timing diagrams (continued) t spr t arw asynchronous reset input registered output clock t ard t arr synchronous preset input clock registered output asynchronous reset synchronous preset t is t ih t cko sp00021
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 14 register preload function (diagnostic mode only) in order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the plc18v8z series device. this feature enables the user to load the registers with predetermined states while a super voltage is applied to pins 11 and 6 (i9/oe and i5). (see diagram for timing and sequence.) to read the data out, pins 11 and 6 must be returned to normal ttl levels. the outputs, f0 f7, must be enabled in order to read data out. the q outputs of the registers will reflect data in as input via f0 f7 during preload. subsequently, the register q output via the feedback path will reflect the data in as input via f0 f7. refer to the voltage waveform for timing and voltage references. t pl = 10 m sec. register preload (diagnostic mode) i 9 / oe (pin 11) i 5 (pin 6) i 0 / clk (pin 1) f 07 i 14 , 68 preload data in preload data out data out oe (v ol ) i 0 / clk f 07 i 14 , 68 t pl t pl t pl t pl t pl t pl t oe t ckl t cko t is t ih 5.0v 5.0v 12.0v 12.0v 12.0v 5.0v sp00022
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 15 logic programming the plc18v8z series is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors' snap design software package. abel ? and cupl ? design software packages also support the plc18v8z architecture. all packages allow boolean and state equation entry formats. snap, abel and cupl also accept, as input, schematic capture format. plc18v8z logic designs can also be generated using the program table entry format, which is detailed on the following pages. this program table entry format is supported by snap only. with logic programming, the and/or/ex-or gate input connections necessary to implement the desired logic function are coded directly from logic equations using the program table. similarly, various omc configurations are implemented by programming the architecture control bits ac1 and ac2. note that the configuration cell is automatically programmed based on the omc configuration. in this table, the logic state of variables i, p and b associated with each sum term s is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows: output polarity (o, b) o , b s x active level code l inverting 1 o, b s x active level code h non-inverting sp00023 aando array (i, b) code state don't care code state code state code state inactive 1 o i, b h i , b l pp p p i, b i , b i, b i, b i , b i, b i, b i , b i, b i, b i , b i, b sp00024 note: 1. a factory shipped unprogrammed device is configured such that all cells are in a conductive state. abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc.
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 16 * the configuration cell is automatically programmed based on the omc architecture. ** for sp, ar: a o is not allowed. t e r m 76543210 76543210 76543210 8 9 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 sp ar pin d a a a a a a a a d a a a a a a a a d a a a a a a a a d a a a a a a a a d a a a a a a a a d a a a a a a a a d a a a a a a a a d a a a a a a a a 11987654321 12 13 14 15 16 17 18 19 12 13 14 15 16 17 18 19 variable name and or (fixed) configuration cell (clk/oe control) i f (i) f (b, o, d) arch. control bits output polarity customer name purchase order # philips device # cf(xxxx) customer symbolized part # total number of parts program table # rev. date notes: in the unprogrammed or virgin state: all and gate locations are pulled to a logic a0o (low). output polarity is inverting. pins 1 and 11 are configured as inputs 0 and 9, respectively, via the configuration cell. the clock and oe functions are disabled. all output macro cells (omc) are configured as combinatorial i/o, with the outputs disabled via the direction control term. inactive i, f (i, b) i, f (i, b) **don't care o h l and array control or array (fixed) ??? ? registered (d-type) fixed input fixed output bidirectional i/o d i o b omc arch. output polarity non-inverting inverting h l config. cell* pin 1 = clk; pin 11 = oe pin 1, pin 11 = input l h data cannot be entered into the or array field due to the fixed nature of the device architec- ture. direction control active output d a not used program table sp00029
philips semiconductors product specification plc18v8z zero standby power cmos versatile pal devices 1997 aug 08 17 snap resource summary designations config. cell config. cell i 0 /clk i 1 i 2 i 7 i 8 programmable and array 36 rows x 72 columns f 6 f 1 f 0 i 9 /oe i 9 f 7 i 0 clk 9 9 9 9 omc oe omc omc omc sp ar ckev8 noutv8 noutv8 noutv8 noutv8 and dinv8 ninv8 oe mux 1 11 clk q oe d f 10 00 01 11 f mux 00 10 11 01 v cc output polarity control from and array s x (n) direction control term to all omcs to all omcs ac1 n ac2 n note: denotes a programmable cell location. from and array sp ar xorinv xordir xorreg noutv8 dffv8 or oe11v8 fdmux sp00025
zero standby power cmos versatile pal devices philips semiconductors product specification plc18v8z 1997 aug 08 18 dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
zero standby power cmos versatile pal devices philips semiconductors product specification plc18v8z 1997 aug 08 19 plcc20: plastic leaded chip carrier; 20 leads sot380-1
zero standby power cmos versatile pal devices philips semiconductors product specification plc18v8z 1997 aug 08 20 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
zero standby power cmos versatile pal devices philips semiconductors product specification plc18v8z 1997 aug 08 21 ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1
zero standby power cmos versatile pal devices philips semiconductors product specification plc18v8z 1997 aug 08 22 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
zero standby power cmos versatile pal devices philips semiconductors product specification plc18v8z 1997 aug 08 23 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. ? copyright philips electronics north america corporation 1997 all rights reserved. printed in u.s.a.

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